. HIGH SPEED
tPD = 15 ns (TYP.) AT VCC =5V
. LOW POWER DISSIPATION
ICC = 4 ?A (MAX.) AT TA = 25 ?C
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = ?IOH? = 4 mA (MIN.)
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS164
DESCRIPTION
The M54/74HC164 is a high speed CMOS 8 BIT
SIPO SHIFT REGISTER fabricated in silicon gate
C2
MOS technology. It has the same highspeed performance of LSTTL combined with true CMOS low
power consumption.
The HC164 is an 8 bit shift register with serial data
entry and an output from each of the eight stages.
Data is entered serially through one of two inputs (A
or B), either of these inputs can be used as an active
high enable for data entry through the other input.
An unused input must be high, or both inputs connected together. Each low-to-high transition on the
clock input shifts data one place to the right and
entersintoQA, thelogic NAND of the twodata inputs
(A ? B), the data that existed before the rising clock
edge. A low level on the clear input overrides all
other inputs and clearsthe register asynchronously,
forcing all Q outputs low.
All inputs are equipped with protection circuits
against static discharge and transient excess voltage