CD4085 DIP IC

Features
? High Voltage Type (20V Rating)
? Medium Speed Operation
– tPHL = 90ns
– tPLH = 125ns (Typ.) at 10V
? Individual Inhibit Controls
? 5V, 10V and 15V Parametric Ratings
? Standardized Symmetrical Output Characteristics
? 100% Tested for Quiescent Current at 20V
? Maximum Input Current of 1?A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
? Noise Margin (Over Full Package/Temperature Range)
– 1V at VDD = 5V
– 2V at VDD = 10V
– 2.5V at VDD = 15V
? Meets All Requirements of JEDEC Tentative Standard
No. 13B, ?Standard Specifications for Description of
?B? Series CMOS Devices?
Description
CD4085BMS contains a pair of AND-OR-INVERT gates, each
consisting of two 2 input AND gates driving a 3 input NOR gate.
Individual inhibit controls are provided for both A-O-I gates..
The CD4085BMS is supplied in these 14 lead outline packages:
Braze Seal DIP H4H
Frit Seal DIP H1B
Ceramic Flatpack H5W