Untitled-design-2020-12-31T103458.132.png

DM7473N DIP IC

Series	7400
Packaging	Tube
Part Status	Obsolete
Function	Set(Preset) and Reset
Type	JK Type
Output Type	Complimentary
Number of Elements	2
Number of Bits per Element	1
Clock Frequency	15MHz
Trigger Type	Positive Edge
Current – Output High, Low	400?A, 16mA
Voltage – Supply	4.75V ~ 5.25V
Operating Temperature	0?C ~ 70?C (TA)
Mounting Type	Through Hole
Supplier Device Package	14-PDIP
Package / Case	14-DIP (0.300″, 7.62mm)
Base Part Number	DM71

General Description
This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops after a complete clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave. The logic states of the J and K
inputs must not be allowed to change while the clock is
HIGH. Data transfers to the outputs on the falling edge of
the clock pulse. A LOW logic level on the clear input will
reset the outputs regardless of the logic states of the other
inp