| Logic Type | Shift Register | |
|---|---|---|
| Output Type | Standard | |
| Number of Elements | 1 | |
| Number of Bits per Element | 8 | |
| Function | Serial to Parallel | |
| Voltage – Supply | 4.75 V ~ 5.25 V | |
| Operating Temperature | 0?C ~ 70?C | |
| Mounting Type | Through Hole | |
| Package / Case | 14-DIP (0.300″, 7.62mm) | |
| Supplier Device Package | 14-PDIP | |
| Base Part Number | 74LS164N |
General?Description?Features
These 8-bit shift registers feature gated serial inputs and ? Gated (enable/disable) serial inputs an asynchronous clear. A low logic level at either input ? Fully buffered clock and serial inputs inhibits entry of the new data, and resets the first flip-flop to ? Asynchronous clear
the low level at the next clock pulse, thus providing com-
plete control over incoming data. A high logic level on ? Typical clock frequency 36 MHz
either input enables the other input, which will then deter- ? Typical power dissipation 80 mW mine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects.