10 years minimum data retention in the absence of external power Data is automatically protected during power loss Directly replaces x 8 volatile static RAM or EEPROM Unlimited write cycles Low-power CMOS JEDEC standard 28-pin DIP package Read and write access times as fast 70 ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Full ?10% VCC operating range (DS1225AD) Optional ?5% VCC operating range (DS1225AB) Optional industrial temperature range to +85?C, designated IND
WE OE VCC GND NC – Address Inputs – Data In/Data Out – Chip Enable – Write Enable – Output Enable – Power (+5V) – Ground – No Connect
The DS1225AB and DS1225AD are 65,536-bit, fully static, nonvolatile SRAMs organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
The DS1225AB and DS1225AD execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13 address inputs (A0 -A12) defines which of the 8192 bytes of data to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than address access.