IS64LP12832-150TQA3

FEATURES
? Internal self-timed write cycle
? Individual Byte Write Control and Global Write
? Clock controlled, registered address, data and
control
? Interleaved or linear burst sequence control
using MODE input
? Three chip enables for simple depth expansion
and address pipelining
? Common data inputs and data outputs
? JEDEC 100-Pin TQFP and
119-pin PBGA package
? Power-down snooze mode
? Power Supply
+ 3.3V VDD
+ 3.3V OR 2.5V VDDQ (I/O)
? Temperature offerings
Option A1: -400 C to +850 C
Option A2: -400 C to +1050 C
Option A3: -400 C to +1250 C

DESCRIPTION
The ISSI IS64LP12832, IS64LP12836, and IS64LP25618
are high-speed synchronous static RAMs designed to
provide high-performance memory with burst for highspeed networking and communication applications.
IS64LP12832 is organized as 131,072 words by 32 bits.
IS64LP12836 is organized as 131,072 words by 36 bits.
IS64LP25618 is organized as 262,144 words by 18 bits. The
IS64LP12832, IS64LP12836, and IS64LP25618 are fabricated with ISSI’s advanced CMOS technology. These
devices integrate a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls
DQc, BW4 controls DQd, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be
written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.