10.00 د.إ
General Description
These universal 9-bit (8 data bits plus 1 parity bit) parity
generators checkers feature odd even outputs and control
inputs to facilitate operation in either odd or even parity ap-
plications Depending on whether even or odd parity is be-
ing generated or checked the even or odd input can be
utilized as the parity or 9th-bit input The word-length capa-
bility is easily expanded by cascading

Input buffers are provided so that each data input repre-
sents only one normalized series 54 74 load A full fan-out
to 10 normalized series 54 74 loads is available from each
of the outputs at a low logic level A fan-out to 20 normal-
ized loads is provided at a high logic level to facilitate the
connection of unused inputs to used inputs
Y? ?174 contains six flip-flops with single-rail outputs
Y? ?175 contains four flip-flops with double-rail outputs
Y? ?Buffered clock and direct clear inputs
Y? ? Individual data input to each flip-flop
Y? ? Applications include:
Buffer/storage registers
Shift registers
Pattern generators
Y? ?Typical clock frequency 40 MHz
Y? ?Typical power dissipation per flip-flop 38 mW
Y? ?Alternate Military/Aerospace device (54174, 54175) is
available. Contact a National Semiconductor Sales Office/Distributor for specifications.

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