SPECIFICATIONS
Mfr Package Description | PLASTIC, DIP-16 |
Status | Transferred |
Logic IC Type | D FLIP-FLOP |
Sub Category | FF/Latches |
Family | 10K |
fmax-Min | 125.0 ?MHz |
JESD-30 Code | R-PDIP-T16 |
JESD-609 Code | e0 |
Max Frequency@Nom-Sup | 1.25E8 ?Hz |
Number of Bits | 1 |
Number of Functions | 2 |
Number of Terminals | 16 |
Operating Temperature-Min | -30.0 ?Cel |
Operating Temperature-Max | 85.0 ?Cel |
Output Characteristics | OPEN-EMITTER |
Output Polarity | COMPLEMENTARY |
Package Body Material | PLASTIC/EPOXY |
Package Code | DIP |
Package Equivalence Code | DIP16,.3 |
Package Shape | RECTANGULAR |
Package Style | IN-LINE |
Peak Reflow Temperature (Cel) | NOT SPECIFIED |
Power Supply Current-Max (ICC) | 62.0 ?mA |
Propagation Delay (tpd) | 5.0 ?ns |
Qualification Status | Not Qualified |
Seated Height-Max | 4.44 ?mm |
Surface Mount | NO |
Technology | ECL |
Temperature Grade | OTHER |
Terminal Finish | Tin/Lead (Sn/Pb) |
Terminal Form | THROUGH-HOLE |
Terminal Pitch | 2.54 ?mm |
Terminal Position | DUAL |
Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
Trigger Type | POSITIVE EDGE |
Length | 19.175 ?mm |
Width | 7.62 ?mm |
Additional Feature | WITH ADDITIONAL COMMON CLOCK |
The MC10131 is a dual master?slave type D flip?flop.
Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flip?flop may be clocked separately by
holding the common clock in the low state and using the enable inputs
for the clocking function. If the common clock is to be used to clock
the flip?flop, the Clock Enable inputs must be in the low state. In this
case, the enable inputs perform the function of controlling the
common clock.
The output states of the flip?flop change on the positive transition of
the clock. A change in the information present at the data (D) input
will not affect the output information at any other time due to master
slave construction.
? PD = 235 mW typ/pkg (No Load)
? FTog = 160 MHz typ
? tpd = 3.0 ns typ
? tr, tf = 2.5 ns typ (20%?80%)