MC10131P DIP IC

10.00 د.إ

SPECIFICATIONS

Mfr Package DescriptionPLASTIC, DIP-16
StatusTransferred
Logic IC TypeD FLIP-FLOP
Sub CategoryFF/Latches
Family10K
fmax-Min125.0 ?MHz
JESD-30 CodeR-PDIP-T16
JESD-609 Codee0
Max Frequency@Nom-Sup1.25E8 ?Hz
Number of Bits1
Number of Functions2
Number of Terminals16
Operating Temperature-Min-30.0 ?Cel
Operating Temperature-Max85.0 ?Cel
Output CharacteristicsOPEN-EMITTER
Output PolarityCOMPLEMENTARY
Package Body MaterialPLASTIC/EPOXY
Package CodeDIP
Package Equivalence CodeDIP16,.3
Package ShapeRECTANGULAR
Package StyleIN-LINE
Peak Reflow Temperature (Cel)NOT SPECIFIED
Power Supply Current-Max (ICC)62.0 ?mA
Propagation Delay (tpd)5.0 ?ns
Qualification StatusNot Qualified
Seated Height-Max4.44 ?mm
Surface MountNO
TechnologyECL
Temperature GradeOTHER
Terminal FinishTin/Lead (Sn/Pb)
Terminal FormTHROUGH-HOLE
Terminal Pitch2.54 ?mm
Terminal PositionDUAL
Time@Peak Reflow Temperature-Max (s)NOT SPECIFIED
Trigger TypePOSITIVE EDGE
Length19.175 ?mm
Width7.62 ?mm
Additional FeatureWITH ADDITIONAL COMMON CLOCK

The MC10131 is a dual master?slave type D flip?flop.
Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flip?flop may be clocked separately by
holding the common clock in the low state and using the enable inputs
for the clocking function. If the common clock is to be used to clock
the flip?flop, the Clock Enable inputs must be in the low state. In this
case, the enable inputs perform the function of controlling the
common clock.
The output states of the flip?flop change on the positive transition of
the clock. A change in the information present at the data (D) input
will not affect the output information at any other time due to master
slave construction.
? PD = 235 mW typ/pkg (No Load)
? FTog = 160 MHz typ
? tpd = 3.0 ns typ
? tr, tf = 2.5 ns typ (20%?80%)

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